30.8.4.7 Power Mode Definition and Power State Table
Note: In Standby mode, if SUPC ->
VREGCTRL.LVSTDBY bit is one, then the regulators output voltage are reduced, and this mode is
called LV Standby mode. In Standby mode, if SUPC -> VREGCTRL.LVHIB bit is one, then the
regulators output voltage are reduced, and this mode is called LV Hibernate mode.
Here is a list of supported mode-to-mode transitions. This list provides a simplified overview of the possible transitions and may not be incomplete.
- ACTIVE -> LV_ACTIVE -> ACTIVE (if CALSUPC.VREGOUTEN is set)
- ACTIVE -> Standby (LV optional) -> ACTIVE
- ACTIVE -> Hibernate (LV optional) -> ACTIVE
- ACTIVE -> Backup -> ACTIVE
- ACTIVE -> OFF -> ACTIVE
| Power Mode Name | Definition Address | Possible next states | NOTES |
|---|---|---|---|
| Active | All clocks running, VDDCORE is nominal | ACTIVE -> Idle, LV Active, Standby, LV Standby, Hibernate, LV Hibernate, Backup, OFF | CPU at maximum frequency in Run Sleepwalking only gates CPU clock |
| Idle | Some clock gating | IDLE -> ACTIVE | CPU at maximum frequency in Run Sleepwalking only gates CPU clock |
| Sleepwalking | CPU clock gating | Sleepwalk -> Standby, Sleepwalk -> LV Standby Sleepwalk -> ACTIVE | Sleepwalking only gates CPU clock |
| LV Active | Reduced Vddcore | ACTIVE | User SW controlled for VREGCTRL voltage and clock frequency (Fuse enabled). Exit to full Run must wait for VREGS to stabilize before WAIT instruction. Maximum CPU frequency less then 8 MHz |
| Standby | Everything is clock gated | ACTIVE, Sleepwalk | Peripheral clocks are on demand |
| LV Standby | Reduced Vddcore Everything is clock gated BG in LP Duty Cycle mode | ACTIVE, Sleepwalk | Longer delay to exit to ACTIVE or Sleepwalk state |
| Hibernate | Only Backup domain and SYS RAM powered | ACTIVE | |
| LV Hibernate | Reduced Vddcore Only Backup domain and SYS RAM powered BG in LP Duty Cycle Mode | ACTIVE | |
| Backup | Only Backup domain is powered | ACTIVE | |
| Off | Only pads are powered | ACTIVE | Only wake up is from RESET pin |