33.2.6.5 ECC Control Bits

Table 33-5. ECC Control Bits
Error Correction Mode	ECCCTL[1:0]	Write Value CTL[2:0]	Read Values CTL[2:0]	Operation
Bypass Mode	2’b11	3’b000	Ignore	Quad Write w/ ECC Read w/o ECC Check
Bypass Mode	2’b11	3’b111	Ignore	Single Write w/ Parity Read w/o Parity Check
ECC Write Dynamic Read Mode	2’b10	3’b000	3’b000 3’b001 3’b010 3’b100	Quad Write w/ ECC Read w/ ECC
ECC Write Dynamic Read Mode	2’b10	3’b111	3’b111 3’b110 3’b101 3’b011	Single Write Not Available Read w/ Parity
Dynamic Mode	2’b01	3’b000	3’b000 3’b001 3’b010 3’b100	Quad Write w/ ECC Read w/ ECC
Dynamic Mode	2’b01	3’b111	3’b111 3’b110 3’b101 3’b011	Single Write w/ Parity Read w/ Parity
ECC Strict Mode	2’b00	3’b000	Ignore	Quad Write w/ ECC Read w/ ECC
ECC Strict Mode	2’b00	N/A	N/A	Single Write is not available All reads use ECC.
Note: If switching modes, Single Writes in Bypass or Dynamic cause SEC and DED errors in ECC mode. It is highly recommend to select and use only one Error Correction Mode.