1.2.1 Floating-Point Unit Registers

The PIC32A Floating-Point Unit (FPU) provides a large set of Working registers (F-regs):

  • 32 x 32-bit (Single Precision, F0 ... F31) or
  • 16 x 64-bit (Double Precision, F0, F2 ... F28, F30) or
  • A mix of the two sizes aligned as shown in Figure 1-2.

In addition to the F-regs, status (FSR) and control (FCR) registers are also supported as shown in Figure 1-2:

  • FSR (FPU Status Register, 32-bit): Holds the status of retired floating-point instructions:
    • FSR[6:0]: Instruction “most-recent” exception status
    • FSR[14:8]: Instruction "sticky" exception status
    • FSR[19:16]: CPS/CPQ instruction status
    • FSR[28:24]: FTST instruction status
  • FCR (FPU Control Register, 16-bit):
    • FCR[6:0]: Exception mask control
    • FCR[9:8]: Rounding mode control
    • FCR[10]: Subnormal result “Flush to Zero” (FTZ) control
    • FCR[11]: Subnormal operand “Subnormals are Zeros” (SAZ) control
  • • FEAR: (FPU Exception Address Capture Register, 24-bit):
    • Holds the address of the first instruction encountered that causes an exception. All subsequent instructions in the FPU pipeline that subsequently retire will not affect the FEAR, even if they too generate exceptions.
Figure 1-2. FPU Programmer’s Model
Note: Only a single register context shown.