39.7 I/O Pins

Table 39-6.  I/O Pin Specifications (1) (5)
SymbolDescriptionMin.Typ.✝ Max.UnitsConditions
Input Low Voltage
VILI/O PORT:
  • With Schmitt Trigger buffer
——0.2 × VDDVINLVL = 0x00
  • With Low-Voltage Buffer (LVBUF)
——< 0.8V

VDD > 2.7V

INLVL = 0x01

TWI PORT:
  • With I2C levels
——0.3 × VDDVTWI CTRLA.INPUTLVL = 0x0
  • With SMBus 3.0 levels
0.8VTWI CTRLA.INPUTLVL = 0x1
RESET Pin——0.2 × VDDV
Input High Voltage
VIHI/O PORT:
  • With Schmitt Trigger buffer
0.8 × VDD——VINLVL = 0x00
  • With Low-Voltage Buffer (LVBUF)
—> 2.0—V

INLVL = 0x01

VDD > 2.7V

TWI PORT:
  • With I2C levels
0.7 × VDD——VTWI CTRLA.INPUTLVL = 0x0
  • With SMBus 3.0 levels
1.35——VTWI CTRLA.INPUTLVL = 0x1

0°C ≤ TA ≤ +125°C,

2.5V ≤ VDD ≤ 5.5V

1.45——VCTRLA.INPUTLVL = 0x1

0°C ≤ TA ≤ +125°C,

1.8V ≤ VDD ≤ 5.5V

RESET Pin0.8 × VDD——V
Input Leakage Current(2)
IILI/O PORTS(3)—±5±125nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

—±5±1000nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA = 125°C

RESET Pin(4) *—±50±200nAGND ≤ VPIN ≤ VDD,

pin at high-impedance, TA= 85°C

Pull-up Current
IPUR90150200μAVDD = 3.0V, VPIN = GND
Output Low Voltage
VOLStandard I/O Ports——0.6VIOL = 10 mA, VDD = 3.0V
Output High Voltage
VOHStandard I/O PortsVDD - 0.7——VIOH = 6 mA, VDD = 3.0V
I/O Slew Rate
tSRRising slew rate—22—nsPORTCTRL.SRL = 0x00
Rising slew rate—45—nsPORTCTRL.SRL = 0x01
Falling slew rate—30—nsPORTCTRL.SRL = 0x01
Falling slew rate—16—nsPORTCTRL.SRL = 0x00
Pin Capacitance
CIOOPAMP output—9—pF
VREFpin—7—pF
XTAL pins—4—pF
Other pins—4—pF

✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:
  1. These figures are valid for all I/O ports regardless of if they are connected to the VDD or VDDIO2 power domain.
  2. The negative current is the current sourced by the pin.
  3. The leakage current numbers for I/O PORTS are valid also when the pin is used as an input to an enabled analog peripheral.
  4. The leakage current on the RESET pin strongly depends on the applied voltage level. The specified levels represent normal operating conditions. A higher leakage current may be measured at different input voltages.
  5. Input voltage threshold is relative to VDDIO2 on MVIO pins (PORTC) and VDD on other pins.