39.4 Supply Voltage

Table 39-3. Supply Voltage
SymbolMin.Typ. ✝Max.UnitsConditions
Supply Voltage(1)
VDD

1.8

—

5.5

V

VDDIO2

1.62

—

5.5

V

Slew Rate——0.25V/µs1.8V ≤ VDD ≤ 5.5V
RAM Data Retention(2)
VDR

1.7

—

—

V

Device in Power-Down mode
Power-on Reset Release Voltage(4)
VPOR

—

1.6

1.8

V

BOD disabled(3)
tPOR

—

1

—

μs

BOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR

—

1.25

—

V

BOD disabled(3)
tPORR

—

2.7

—

μs

BOD disabled(3)
VDD Rise Rate to Ensure Internal Power-on Reset Signal(4)
SVDD *0.05

—

—

V/msBOD disabled(3)

✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. If the supply voltage VDD is below VBOD for BODLEVEL0, the erase attempt will fail.
  2. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  3. Refer to section RSTCTRL for BOD trip point information.
  4. Refer to Figure 39-1.
Figure 39-1. POR and PORR with Slow Rising VDD
Note:
  • When POR is low, the device is held in Reset