5.2 Place and Route

To place and route the design, TX_PLL, XCVR_REF_CLK, and PF_XCVR are configured using the I/O Editor. To configure the components and place and route the design, perform the following steps:

  1. On the Design Flow window, double-click Manage Constraints.
  2. On the I/O Attributes tab, click Edit with I/O Editor, as shown in the following figure.
    Figure 5-2. Edit with I/O Editor Option
  3. Using the XCVR View in I/O Editor, place TX_PLL, XCVR_REF_CLK, and PF_XCVR TX as shown in the following figure.
    Figure 5-3. I/O Editor Transceiver View

    The Signal Integrity View for LANEO_TXD_P/N and LANE0_RX_P/N is shown in the following figure.

    Figure 5-4. Signal Integrity View
  4. When all the components are placed, the location of the components is updated in the user_fp.pdc file (located in Constraint Manager > Floor planner tab), as shown in the user_fp.pdc file.
    set_location -inst_name BASEKR_IP_0_inst_0/TX_PLL/PF_TX_PLL_C0_0/txpll_inst_0 -fixed true -x 2460 -y 320
set_location -inst_name BASEKR_IP_0_inst_0/XCVR_ERM/I_XCVR/LANE0 -fixed true -x 2460 -y 317
set_location -inst_name BASEKR_IP_0_inst_0/XCVR_RF_CLK/XCVR_RF_CLK_0_0/I_IO -fixed true -x 2466 -y 317
  5. On the Design Flow window, double-click Place and Route. When place and route is successful, a green tick mark appears next to Place and Route, as shown in Figure 5-1.
  6. Right-click Place and Route and select View Report to view the place and route report and log files in the Reports tab. View the BASEKR_TOP_place_and_route_constraint_coverage.html file for place and route constraint coverage.