3 Demo Design
(Ask a Question)The Core10GBaseKR_PHY interfaces XGMII compliant MAC with the 10GBaseKR device for the backplane applications. The IP designed is as per the IEEE 802.3-2012 specification and supports XGMII interface towards (MAC side) and PMA interface to the SerDes side. For the 10GBaseKR applications, the transceiver is used in PMA native mode (32-bit only) and connected to the Ethernet MAC through the PCS interface.
For 10GBASEKR configuration, the Link Training and Auto-Negotiation blocks are enabled, and they are accessed from the 32-bit APB slave interface. The provision to disable the Auto-Negotiation and Link Training is provided through parameter static configuration as part of this IP.
Microchip FPGA board interacts with Vitesse SparX-5i board through SFP interface.
- CORE10GMAC: Serves as a 10 Gbps Ethernet MAC that transmits and receives the Ethernet packets
- Transceiver: Acts as a 10GBASEKR physical interface for data transfers; configured for 64b/66b encoding/decoding with scrambler/descrambler enabled with a PCS interface width of 32 bits to the CORE10GMAC
- MIV_RV32 (Soft Processor): Configures the CORE10G_BASEKR registers
- PF_TX_PLL: Generates the bit clock required for the transceiver
- PF_XCVR_REF_CLK: Generates the fabric clock and the reference clock for the transceiver and the TX_PLL
- BaseKRPHY: Implements BASE-KR functionality
The following table lists the clock frequencies used in the design.
| Clock | Frequency (MHz) |
|---|---|
| CDR reference clock | 156.25 |
| Transceiver bit clock | 5156.25 |
| I_SYS_CLOCK | 156.25 |
| I_CORE_TX_CLK | 322.26 |
| I_CORE_RX_CLK | 322.26 |
| PCLK | 50 |
The following figure shows the top-level block diagram of the PolarFire 10GBASEKR hardware implementation.
