3.3 Clocking Structure

  • The Clock to the transceiver PF_XCVR is provided by the TX_PLL, the reference clock to the TX_PLL (PF_XCVR_TXPLL, as in block diagram) is sourced from the on-board crystal of 156.25 MHz
  • The FAB_REF_CLK is provided as the reference clock to the CCC and the clock of 50 MHz (OUT1) and 156.25 MHz (OUT0) is generated
  • The OUT1 is connected as PCLK for Mi-V, Core10GMAC, Core10GBaseKR PHY, and Packet generator and Checker
  • The OUT0 clock output of the CCC is connected to Core10GMAC clock inputs, Core10GBaseKR_PHY XGMII clock inputs, and the Packet generator and Checker clock input
  • RX_CLK_R is the recovered clock output of the PF_XCVR, and connects to I_RX_CLK and I_PCS73_RX_CLK inputs of Core10GBaseKR_PHY
  • TX_CLK_R is the transmit clock output of PF_XCVR, and connects to I_TX_CLK and I_PCS73_TX_CLK inputs of Core10GBaseKR_PHY

The clocking structure of the design is shown in the following figure.

Figure 3-12. Clocking Structure