3.2 Design Blocks and IP Configuration
(Ask a Question)The following IPs are configured before implementing the demo design:
- Core10GMAC
- BaseKR_PHY
- Transceiver Interface
- Transmit PLL
- Transceiver Reference Clock
- MIV_RV32
- CoreAPB3
- PF_POWER_INIT
- PF_CCC_0