7.7.14 PIR3

Peripheral Interrupt Request (Flag) Register 3

Note:
  1. The RCnIF flag is a read-only bit. To clear the RCnIF flag, the firmware must read from RCnREG enough times to remove all bytes from the receive buffer.
  2. The TXnIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXnIF flag, the firmware must write enough data to TXnREG to completely fill all available bytes in the buffer. The TXnIF flag does not indicate transmit completion (use TRMT for this purpose instead).
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
Name: PIR3
Offset: 0x70F

Bit 76543210 
   RC1IFTX1IF  BCL1IFSSP1IF 
Access RO/HSRO/HSR/W/HSR/W/HS 
Reset 0000 

Bit 5 – RCnIF  EUSARTn Receive Interrupt Flag bit(1)

ValueDescription
1 The EUSARTn receive buffer is not empty (contains at least one byte)
0 The EUSARTn receive buffer is empty

Bit 4 – TXnIF  EUSARTn Transmit Interrupt Flag bit(2)

ValueDescription
1 The EUSARTn transmit buffer contains at least one unoccupied space
0 The EUSARTn transmit buffer is currently full. The application firmware must not write to TXnREG again, until more room becomes available in the transmit buffer.

Bit 1 – BCLnIF MSSPn Bus Collision Interrupt Flag bit

ValueDescription
1 A bus collision was detected (must be cleared in software)
0 No bus collision was detected

Bit 0 – SSPnIF Synchronous Serial Port ‘n’ Interrupt Flag bit

ValueDescription
1 The Transmission/Reception/Bus condition is complete (must be cleared in software)
0 Waiting for the Transmission/Reception/Bus condition in progress
The RCnIF flag is a read-only bit. To clear the RCnIF flag, the firmware must read from RCnREG enough times to remove all bytes from the receive buffer. The TXnIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXnIF flag, the firmware must write enough data to TXnREG to completely fill all available bytes in the buffer. The TXnIF flag does not indicate transmit completion (use TRMT for this purpose instead). Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.