7.7.13 PIR2
Peripheral Interrupt Request (Flag) Register 2
Note: Interrupt flag bits are set when an Interrupt condition occurs,
regardless of the state of its corresponding enable bit or the
Global Enable bit. User software must ensure the appropriate
interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
| Name: | PIR2 |
| Offset: | 0x70E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZCDIF | C2IF | C1IF | |||||||
| Access | R/W/HS | R/W/HS | R/W/HS | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – ZCDIF Zero-Cross Detect Interrupt Flag bit
| Value | Description |
|---|---|
1 |
An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software) |
0 |
No ZCD1 event has occurred |
Bits 0, 1 – CnIF Comparator ‘n’ Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Comparator Cn interrupt asserted (must be cleared in software) |
0 |
Comparator Cn interrupt not asserted |