7.7.18 PIR7
Peripheral Interrupt Request (Flag) Register 7
Note: Interrupt flag bits are set when an Interrupt condition occurs,
regardless of the state of its corresponding enable bit or the
Global Enable bit. User software must ensure the appropriate
interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
| Name: | PIR7 |
| Offset: | 0x713 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMIF | NCO1IF | CWG2IF | CWG1IF | ||||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 5 – NVMIF NVM Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The requested NVM operation has completed |
0 |
NVM interrupt not asserted |
Bit 4 – NCO1IF Numerically Controlled Oscillator (NCO) Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The NCO has rolled over |
0 |
No NCO interrupt event has occurred |
Bit 1 – CWG2IF CWG2 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
CWG2 has gone into shutdown |
0 |
CWG2 is operating normally, or interrupt cleared |
Bit 0 – CWG1IF CWG1 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
CWG1 has gone into shutdown |
0 |
CWG1 is operating normally, or interrupt cleared |