7.7.12 PIR1
Peripheral Interrupt Request (Flag) Register 1
Note: Interrupt flag bits are set when an Interrupt condition occurs,
regardless of the state of its corresponding enable bit or the
Global Enable bit. User software must ensure the appropriate
interrupt flag bits are clear prior to enabling an interrupt. This
feature allows for software polling.
| Name: | PIR1 |
| Offset: | 0x70D |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSFIF | CSWIF | ADTIF | ADIF | ||||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – OSFIF Oscillator Fail Interrupt Flag bit
| Value | Description |
|---|---|
1 |
Oscillator fail-safe interrupt has occurred (must be cleared in software) |
0 |
No oscillator fail-safe interrupt |
Bit 6 – CSWIF Clock-Switch Complete Interrupt Flag bit
| Value | Description |
|---|---|
1 |
The clock switch module indicates an Interrupt condition and is ready to complete the clock switch operation (must be cleared in software) |
0 |
The clock switch does not indicate an Interrupt condition |
Bit 1 – ADTIF ADC Threshold Interrupt Flag bit
| Value | Description |
|---|---|
1 |
An A/D conversion or complex operation has completed (must be cleared in software) |
0 |
An A/D conversion or complex operation is not complete |
Bit 0 – ADIF ADC Interrupt Flag bit
| Value | Description |
|---|---|
1 |
An A/D conversion or complex operation has completed (must be cleared in software) |
0 |
An A/D conversion or complex operation is not complete |