44.4.5 Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications

Figure 44-7. Reset, Watchdog Timer, and Power-up Timer Timing
Note:
  1. Asserted low.
Figure 44-8. Brown-out Reset Timing and Characteristics
Note:
  1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.
Table 44-11. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
RST01*TMCLRMCLR Pulse-Width Low to ensure Reset—0.6—μs
RST02*TIOZI/O high-impedance from Reset detection——2μs
RST03*TWDTWatchdog Timer Time-out Period—16—msWDTCPS = 'b00100
RST04*TPWRTPower-up Timer Period—65—msPWRTS = 'b10
RST05*TOSTOscillator Start-up Timer Period(1,2)—1024—TOSC
RST06VBORBrown-out Reset Voltage2.52.652.85VBORV = 0
RST06A1.81.92.1VBORV = 1
RST07*VBORHYSBrown-out Reset Hysteresis—35—mVBORV = 0
RST08*TBORDCBrown-out Reset Response Time—1—μs
RST09*VLPBORLow-Power Brown-out Reset Voltage1.81.92.5V
RST10*VLPBORHYSLow-Power Brown-out Reset Hysteresis—25—mV

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated.

* These parameters are characterized but not tested.

Note:
  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
  2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.