25.3.8 SMTxCLK

SMT Clock Selection Register

Name:	SMTxCLK
Offset:	0xF19,0xF07


Bit	7	6	5	4	3	2	1	0
						CSEL[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0

Bits 2:0 – CSEL[2:0] SMT Clock Selection bits

Table 25-2. SMT Clock Source Selection
CSEL[2:0]	Clock Source
`111`	CLKREF output
`110`	SOSC
`101`	MFINTOSC/16 (31.25kHz)
`100`	MFINTOSC (500kHz)
`011`	LFINTOSC
`010`	HFINTOSC
`001`	F_OSC
`000`	F_OSC/4

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