25.2 Register Summary - SMT Control


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x0EF7	Reserved
0x0EF8	SMT2TMR	7:0	TMR[7:0]
		15:8	TMR[15:8]
		23:16	TMR[23:16]
0x0EFB	SMT2CPR	7:0	CPR[7:0]
		15:8	CPR[15:8]
		23:16	CPR[23:16]
0x0EFE	SMT2CPW	7:0	CPW[7:0]
		15:8	CPW[15:8]
		23:16	CPW[23:16]
0x0F01	SMT2PR	7:0	PR[7:0]
		15:8	PR[15:8]
		23:16	PR[23:16]
0x0F04	SMT2CON0	7:0	EN		STP	WPOL	SPOL	CPOL	PS[1:0]
0x0F05	SMT2CON1	7:0	GO	REPEAT			MODE[3:0]
0x0F06	SMT2STAT	7:0	CPRUP	CPWUP		RST		TS	WS	AS
0x0F07	SMT2CLK	7:0						CSEL[2:0]
0x0F08	SMT2SIG	7:0				SSEL[4:0]
0x0F09	SMT2WIN	7:0				WSEL[4:0]
0x0F0A	SMT1TMR	7:0	TMR[7:0]
		15:8	TMR[15:8]
		23:16	TMR[23:16]
0x0F0D	SMT1CPR	7:0	CPR[7:0]
		15:8	CPR[15:8]
		23:16	CPR[23:16]
0x0F10	SMT1CPW	7:0	CPW[7:0]
		15:8	CPW[15:8]
		23:16	CPW[23:16]
0x0F13	SMT1PR	7:0	PR[7:0]
		15:8	PR[15:8]
		23:16	PR[23:16]
0x0F16	SMT1CON0	7:0	EN		STP	WPOL	SPOL	CPOL	PS[1:0]
0x0F17	SMT1CON1	7:0	GO	REPEAT			MODE[3:0]
0x0F18	SMT1STAT	7:0	CPRUP	CPWUP		RST		TS	WS	AS
0x0F19	SMT1CLK	7:0						CSEL[2:0]
0x0F1A	SMT1SIG	7:0				SSEL[4:0]
0x0F1B	SMT1WIN	7:0				WSEL[4:0]