Reading CSI_INT_ST_PKT does not clear the interrupt pin.
The following configuration values are valid for all listed bit names of this
register:
0: No event occurred since the last read of the register.
1: An event occurred since the last read of the register.
Name:
CSI_INT_ST_PKT
Offset:
0x120
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
VC3_ERR_ECC_CORRECTED
VC2_ERR_ECC_CORRECTED
VC1_ERR_ECC_CORRECTED
VC0_ERR_ECC_CORRECTED
Access
R
R
R
R
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
ERR_ID_VC3
ERR_ID_VC2
ERR_ID_VC1
ERR_ID_VC0
Access
R
R
R
R
Reset
0
0
0
0
Bit 19 – VC3_ERR_ECC_CORRECTED Header Error
Detected and Corrected on Virtual Channel 3 (cleared on read)
Bit 18 – VC2_ERR_ECC_CORRECTED Header Error
Detected and Corrected on Virtual Channel 2 (cleared on read)
Bit 17 – VC1_ERR_ECC_CORRECTED Header Error Detected and Corrected on Virtual Channel 1 (cleared
on read)
Bit 16 – VC0_ERR_ECC_CORRECTED Header Error Detected and
Corrected on Virtual Channel 0 (cleared on read)
Bit 3 – ERR_ID_VC3 Unrecognized or
Unimplemented Data Type Detected in Virtual Channel 3 (cleared on read)
Bit 2 – ERR_ID_VC2 Unrecognized or
Unimplemented Data Type Detected in Virtual Channel 2 (cleared on
read)
Bit 1 – ERR_ID_VC1 Unrecognized or
Unimplemented Data Type Detected in Virtual Channel 1 (cleared on
read)
Bit 0 – ERR_ID_VC0 Unrecognized or
Unimplemented Data Type Detected in Virtual Channel 0 (cleared on read)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
