Used for test purposes. Triggers CSI_INT_ST_PKT_FATAL interrupt events individually without the
need to activate the conditions that trigger the interrupt sources.
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: The corresponding interrupt source is forced.
Name:
CSI_INT_FORCE_PKT_FATAL
Offset:
0xF8
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
FORCE_ERR_ECC_DOUBLE
Access
R/W
Reset
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
FORCE_VC3_ERR_CRC
FORCE_VC2_ERR_CRC
FORCE_VC1_ERR_CRC
FORCE_VC0_ERR_CRC
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit 16 – FORCE_ERR_ECC_DOUBLE Force Header ECC Double
Error Interrupt
Bit 3 – FORCE_VC3_ERR_CRC Force Virtual
Channel 3 Payload Checksum Error Interrupt
Bit 2 – FORCE_VC2_ERR_CRC Force Virtual
Channel 2 Payload Checksum Error Interrupt
Bit 1 – FORCE_VC1_ERR_CRC Force Virtual Channel 1 Payload Checksum Error
Interrupt
Bit 0 – FORCE_VC0_ERR_CRC Force Virtual Channel 0
Payload Checksum Error Interrupt
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
