Used for test purposes. Triggers INT_ST_PHY interrupt events individually without the need to
activate the conditions that trigger the interrupt sources.
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: The corresponding interrupt source is forced.
Name:
CSI_INT_FORCE_PHY
Offset:
0x118
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
FORCE_PHY_ERRESC_1
FORCE_PHY_ERRESC_0
Access
R/W
R/W
Reset
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
FORCE_PHY_ERRSOTHS_1
FORCE_PHY_ERRSOTHS_0
Access
R/W
R/W
Reset
0
0
Bit 17 – FORCE_PHY_ERRESC_1 Force Start of Transmission Error on Data Lane 1 (synchronization
can still be achieved) Interrupt
Bit 16 – FORCE_PHY_ERRESC_0 Force Start of Transmission
Error on Data Lane 0 (synchronization can still be achieved)
Interrupt
Bit 1 – FORCE_PHY_ERRSOTHS_1 Force Start of Transmission Error on Data Lane 1 (no
synchronization achieved) Interrupt
Bit 0 – FORCE_PHY_ERRSOTHS_0 Force Start of Transmission
Error on Data Lane 0 (no synchronization achieved) Interrupt
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
