7.7.6.12 ASRC Interrupt Mask Register of Stereo Channel x

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

Name: ASRC_IMRx
Offset: 0x88 + x*0x04 [x=0..3]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
  LOCK       
Access R 
Reset 0 
Bit 2322212019181716 
        SECE 
Access R 
Reset 0 
Bit 15141312111098 
   TXOVRTXUDRTXCHUNKTXFULLTXEMPTYTXRDY 
Access RRRRRR 
Reset 000000 
Bit 76543210 
   RXOVRRXUDRRXCHUNKRXFULLRXEMPTYRXRDY 
Access RRRRRR 
Reset 000000 

Bit 30 – LOCK DPLL Locked Interrupt Mask

Bit 16 – SECE Security/Safety Report Interrupt Mask

Bit 13 – TXOVR Transmit Over Flow Interrupt Mask

Bit 12 – TXUDR Transmit Under Flow Interrupt Mask

Bit 11 – TXCHUNK Transmit FIFO Chunk Interrupt Mask

Bit 10 – TXFULL Transmit FIFO Full Interrupt Mask

Bit 9 – TXEMPTY Transmit FIFO Empty Interrupt Mask

Bit 8 – TXRDY Transmit Ready Interrupt Mask

Bit 5 – RXOVR Receive Over Flow Interrupt Mask

Bit 4 – RXUDR Receive Under Flow Interrupt Mask

Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Mask

Bit 2 – RXFULL Receive FIFO Full Interrupt Mask

Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Mask

Bit 0 – RXRDY Receive Ready Interrupt Mask