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7.5.7.8 SPDIF Transmitter Interrupt Disable
Register This register can only be written if the WPITEN bit is cleared in the SPDIFTX Write Protection Mode Register .
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name: SPDIFTX_IDR Offset: 0x18 Reset: – Property: Write-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 BEND SECE Access W W Reset – –
Bit 7 6 5 4 3 2 1 0 UDRDY CSRDY TXOVR TXUDR TXCHUNK TXFULL TXEMPTY TXRDY Access W W W W W W W W Reset – – – – – – – –
Bit 13 – BEND Block End Interrupt Disable
Bit 10 – SECE Security Report Interrupt Disable
Bit 7 – UDRDY User Data Ready Interrupt Disable
Bit 6 – CSRDY Channel Status Ready Interrupt Disable
Bit 5 – TXOVR Transmit Over Flow Interrupt Disable
Bit 4 – TXUDR Transmit Under Flow Interrupt Disable
Bit 3 – TXCHUNK Transmit FIFO Chunk Size Empty Interrupt Disable
Bit 2 – TXFULL Transmit FIFO Full Interrupt Disable
Bit 1 – TXEMPTY Transmit FIFO Empty Interrupt Disable
Bit 0 – TXRDY Transmit Ready Interrupt Disable
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