7.5.7.7 SPDIF Transmitter Interrupt Enable Register

This register can only be written if the WPITEN bit is cleared in the SPDIFTX Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: SPDIFTX_IER
Offset: 0x14
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   BEND  SECE   
Access WW 
Reset –– 
Bit 76543210 
 UDRDYCSRDYTXOVRTXUDRTXCHUNKTXFULLTXEMPTYTXRDY 
Access WWWWWWWW 
Reset –––––––– 

Bit 13 – BEND Block End Interrupt Enable

Bit 10 – SECE Security Report Interrupt Enable

Bit 7 – UDRDY User Data Ready Interrupt Enable

Bit 6 – CSRDY Channel Status Ready Interrupt Enable

Bit 5 – TXOVR Transmit Over Flow Interrupt Enable

Bit 4 – TXUDR Transmit Under Flow Interrupt Enable

Bit 3 – TXCHUNK Transmit FIFO Chunk Size Empty Interrupt Enable

Bit 2 – TXFULL Transmit FIFO Full Interrupt Enable

Bit 1 – TXEMPTY Transmit FIFO Empty Interrupt Enable

Bit 0 – TXRDY Transmit Ready Interrupt Enable