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7.5.7.9 SPDIF Transmitter Interrupt Mask
Register The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name: SPDIFTX_IMR Offset: 0x1C Reset: 0x00000000 Property: Read-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 BEND SECE Access W R Reset 0 0
Bit 7 6 5 4 3 2 1 0 UDRDY CSRDY TXOVR TXUDR TXCHUNK TXFULL TXEMPTY TXRDY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 13 – BEND Block End Interrupt Mask
Bit 10 – SECE Security Report Interrupt Mask
Bit 7 – UDRDY User Data Ready Interrupt Mask
Bit 6 – CSRDY Channel Status Ready Interrupt Mask
Bit 5 – TXOVR Transmit Over Flow Interrupt Mask
Bit 4 – TXUDR Transmit Under Flow Interrupt Mask
Bit 3 – TXCHUNK Transmit FIFO Chunk Size Empty Interrupt Mask
Bit 2 – TXFULL Transmit FIFO Full Interrupt Mask
Bit 1 – TXEMPTY Transmit FIFO Empty Interrupt Mask
Bit 0 – TXRDY Transmit Ready Interrupt Mask
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