7.5.7.14 SPDIF Transmitter Channel 1 Status Register
x
Name:
SPDIFTX_CH1Sx
Offset:
0x80 + x*0x04 [x=0..5]
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
CHS[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CHS[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CHS[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CHS[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – CHS[31:0] Channel 1 Status Word x
The six 32-bit Channel
Status registers contain the 192-bit Channel Status sent to channel
1.
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