2.3 Pinout Description

The ATWINC15x0B pins with default peripheral mapping are described in the following table.

Table 2-1. ATWINC15x0B Pin Description
Pin Number	Pin Name	Pin Type	Description
1	TP_P	Analog	Test pin/no connect
2	VDD_RF_RX	Power	Tuner RF supply⁽¹⁾
3	VDD_AMS	Power	Tuner BB supply⁽¹⁾
4	VDD_RF_TX	Power	Tuner RF supply⁽¹⁾
5	VDD_BATT_PPA	Power	PA 1st stage supply⁽¹⁾
6	VDD_VBATT_PA	Power	PA 2nd stage supply⁽¹⁾
7	RFIOP	Analog	Positive RF differential I/O
8	RFION	Analog	Negative RF differential I/O
9	SPI_CFG	Digital Input	Tie to VDDIO through a 1 MΩ resistor to enable the SPI interface
10	GPIO0	Digital I/O, Programmable Pull-Up	GPIO0⁽²⁾
11	GPIO2/IRQN	Digital I/O, Programmable Pull-Up	GPIO2⁽²⁾/ATWINC15x0B interrupt output; connect to host interrupt input pin
12	UART_TXD	Digital I/O, Programmable Pull-Up	UART transmit output from ATWINC15x0B; added for debug and testing only
13	SPI_RXD	Digital I/O, Programmable Pull-Up	SPI MOSI (Master Out, Slave In) pin
14	VDDC	Power	Digital core power supply⁽¹⁾
15	VDDIO	Power	Digital I/O power supply⁽¹⁾
16	SPI_SSN	Digital I/O, Programmable Pull-Up	SPI slave select (active-low)
17	SPI_TXD	Digital I/O, Programmable Pull-Up	SPI MISO (Master In, Slave Out) pin
18	SPI_SCK	Digital I/O, Programmable Pull-Up	SPI clock
19	UART_RXD	Digital I/O, Programmable Pull-Up	UART receive input to ATWINC15x0B; added for debug and testing only
20	VBATT_BUCK	Power	Battery supply for DC/DC converter⁽¹⁾
21	VSW	Power	Switching output of DC/DC converter⁽¹⁾
22	VREG_BUCK	Power	Core power from DC/DC converter⁽¹⁾ Decouple with 10 µF and 0.01 µF capacitor to GND and place these capacitors as recommended in Power Management Unit
23	CHIP_EN	Analog	Module enable pin High level enables the module and low level places module in Power-Down mode By default, connect a host output to low at power-up; if the host output is tristated, add a 1 MΩ pull-down resistor to ensure a low level at power-up
24	GPIO1/RTC_CLK	Digital I/O, Programmable Pull-Up	GPIO1/32 kHz clock input⁽²⁾
25	TEST_MODE	Digital Input	Test mode – User must tie this pin to GND
26	VDDIO	Power	Digital I/O power supply⁽¹⁾
27	VDDC	Power	Digital core power supply⁽¹⁾
28	GPIO3	Digital I/O, Programmable Pull-Up	GPIO3⁽²⁾
29	GPIO4	Digital I/O, Programmable Pull-Up	GPIO4⁽²⁾
30	GPIO5	Digital I/O, Programmable Pull-Up	GPIO5⁽²⁾
31	GPIO6	Digital I/O, Programmable Pull-Up	GPIO6⁽²⁾
32	I2C_SCL	Digital I/O, Programmable Pull-Up	I²C slave clock (high-drive pad, see ATWINC15x0B Electrical Characteristics table) Currently, used only for debug development Leave unconnected It is recommended to add Test Point (TP) to this pin
33	I2C_SDA	Digital I/O, Programmable Pull-Up	I²C slave data (high-drive pad, see ATWINC15x0B Electrical Characteristics table) Currently, used only for debug development Leave unconnected It is recommended to add Test Point (TP) to this pin
34	RESETN	Digital Input	Active-low hard Reset Assert low to put the module in Reset state Assert high to put the module in Normal state and move it out of Reset state By default, connect a host output to low at power-up; if the host output is tri-stated, add a 1 MΩ pull-down resistor to ensure a low level at power-up
35	XO_N	Analog	Crystal oscillator N
36	XO_P	Analog	Crystal oscillator P
37	VDD_SXDIG	Power	SX power supply⁽¹⁾
38	VDD_VCO	Power	VCO power supply⁽¹⁾
39	VDDIO_A	Power	Tuner VDDIO power supply⁽¹⁾
40	TP_N	Analog	Test pin/no connect
41	PADDLE VSS	Power	Connect to system board ground

Note:

For more information, refer to Power Architecture.
Usage of the GPIO functionality is not supported by the ATWINC15x0 firmware. The data sheet will be updated once the support for this feature is added.