4.12.3 Pattern Match Output Pins

When an outbound packet matches the configured transmit match pattern, the device can assert the Transmit Packet Indication (TXPI) signal. Similarly, the Receive Packet Indication (RXPI) signal can be asserted when an inbound packet matches the configured receive match pattern. Alternatively, the Receive/Transmit Packet Indication (RXTXPI) signal can be asserted when an inbound packet or an outbound packet matches the respective patterns. That is, RXTXPI is essentially the logical OR of the TXPI and RXPI internal signals. The station host controller can then use the signals on these pins to generate a time stamp.

The GPIO0 Source Select bit in the Pin Control (PINCTRL) register can be used to select either of the pattern matching signals TXPI, RXPI, or RXTXPI. In addition, the LAN8672 has a dedicated pin for RXPI, and the LAN8670 provides the RXPI signal on a separate pin only when in SC-MII or RMII modes. The TXPI Polarity (TXPIPOL) bit configures whether a rising or falling edge is used on TXPI to indicate a transmit packet match to the host controller. The RXPI Polarity (RXPIPOL) provides the same functionality for a receive patch match. When GPIO0 is configured as RXTXPI, the RXTXPI polarity is configured using the TXPI Polarity (TXPIPOL) bit.

Once the transmit packet pattern matcher is configured, the transmit packet pattern matcher is enabled by setting the Transmit Packet Match Enable (TXME) bit in the Transmit Match Control (TXMCTL) register. When the device detects that a packet being transmitted matches, the TXPI signal will be asserted. Similarly, the receive packet pattern matcher is enabled by setting the Receive Packet Match Enable (RXME) bit in the Receive Match Control (RXMCTL) register.

The pattern match outputs are delayed relative to the end of the Start-of-Stream Delimiter (SSD) as it is present on the pins. This delay has a fixed amount through the analog and digital circuit paths of the device, and a jitter component. See the following table for details.