5.4.3 Pin Control Register

Name: PINCTRL
Address: 0x0011

Bit 15141312111098 
 GPIO0SS[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 10000000 
Bit 76543210 
 TXPIPOL[1:0]RXPIPOL[1:0]ACMAPOL[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:14 – GPIO0SS[1:0] GPIO0 Signal Select

This field configures the GPIO0 signal select. The valid configurations and restrictions for each device and operating mode are shown in Table 5-1.

Table 5-1. GPIO0 Signal Select Restrictions
LAN8670LAN8671LAN8672
GPIO0SSSignalMIISC-MIIRMIIRMIIMII
00RXPI✔ReservedReserved✔Reserved
01TXPI✔✔✔✔✔
10RXTXPI✔✔✔✔✔
11ACMA✔ReservedReserved✔Reserved
ValueDescription
00

Receive packet indication output pulse (RXPI)

01

Transmit packet indication output pulse (TXPI)

10

Receive/Transmit packet indication output pulse (RXTXPI)

11

Application Controlled Media Access input (ACMA)

Bits 7:6 – TXPIPOL[1:0] TXPI Polarity

This field configures the TXPI pin output polarity on a transmit packet indication. Additionally, when GPIO0 is configured as RXTXPI output, this field will configure the output polarity of RXTXPI on indication of a receive or transmit packet.

ValueDescription
00Transmit packet indication on rising edge of 200 ns positive pulse (pin is idle low)
01Transmit packet indication on falling edge of 200 ns negative pulse (pin is idle high)
10Undefined
11Undefined

Bits 5:4 – RXPIPOL[1:0] RXPI Polarity

This field configures the RXPI pin output polarity on a receive packet indication.
ValueDescription
00Receive packet indication on rising edge of 200 ns positive pulse (pin is idle low)
01Receive packet indication on falling edge of 200 ns negative pulse (pin is idle high)
10Undefined
11Undefined

Bits 1:0 – ACMAPOL[1:0] ACMA Polarity

This field configures the polarity of the ACMA pin that enables the PHY to transmit.
ValueDescription
00The PHY will be allowed to transmit when the ACMA pin is asserted high.
01The PHY will be allowed to transmit when the ACMA pin is asserted low.
10Undefined
11Undefined