35.6.4 Serial Clock Baud Rate
The QSPI Baud rate clock is generated by dividing the module clock (CLK_QSPI_AHB) by a value between 1 and 255.
This allows a maximum operating baud rate at up to Host Clock and a minimum operating baud rate of CLK_QSPI_AHB divided by 255.
At reset, BAUD = 0 and the user has to program a valid value before performing the first transfer.