34.6.2.4 I2C Host Operation
The I2C host is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations and a Special Smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN).
The I2C host has two interrupt strategies.
When SCL Stretch Mode (CTRLA.SCLSM) is ‘0’, SCL is stretched before or after the Acknowledge bit . In this mode, the I2C host operates according to Figure 34-5. The circles labeled Mn (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware interaction.
This diagram is used as a reference for the description of the I2C host operation throughout the document.
In the second strategy (CTRLA.SCLSM = 1), interrupts only occur after the ACK bit, as illustrated in Figure 34-6. This strategy can be used when it is not necessary to check DATA before acknowledging.
