18.3.1.7 Extreme Deep Sleep (XDS) Mode

In the Extreme Deep Sleep mode, INT0, which is the external interrupt pin, alone is active and can wake up the device. Exiting XDS is equivalent to POR. The RCON register provides the status whether it is a normal power up or exiting from XDS.

Extreme Deep Sleep Mode Entry

  1. Disable all the interrupts except INT0 (as desired).
  2. Disable RTCC, DSWDT and WCM Retention.
  3. Set the DSEN bit in the DSCON register.
  4. Check for the pending interrupts, then, if present, abort the Extreme Deep Sleep mode and service the interrupt.
  5. If there are no pending interrupts, issue a WFI command from the CPU.

    To minimize the chance of entering the Extreme Deep Sleep mode spuriously, it is recommended that the WFI command be issued as the next instruction following the setting of the DSCON.DSEN bit. This sequence can still be interrupted by interrupts and other system latencies, but it does not prevent the system entering the Extreme Deep Sleep mode once the WFI command is executed.

    The DSEN bit is, then, automatically cleared when exiting the Extreme Deep Sleep mode.

Extreme Deep Sleep Mode Exit

The Extreme Deep Sleep mode exits on any of the following events:
  1. POR event on the VDD supply.
  2. Assertion of the (MCLR) pin or INT0 pin.