18.3.1.5 Standby Sleep Mode

In the Standby Sleep mode, the FlexRAM (SRAM) is in the Retention mode while the CPU and most peripherals are clock gated off and no code is executed.

Standby Sleep Entry

The Standby Sleep mode is entered when DSCON.DSEN is clear and the OSCCON.SLPEN bit is set and the CPU executes a WFI instruction. This causes the device clocks to be held low (‘0’).

Entry into the Standby Sleep mode from any other mode does not require a clock switch. This is due to the fact that when the device is in the Standby Sleep mode, no clocks are required.

Note: If software writes to the CRU SFR before going into the Standby Sleep mode, it is recommended to perform read on the SFR to flush the write before executing the WFI instruction that initiates the Standby Sleep mode.

Standby Sleep Exit

The device comes out of Standby Sleep mode and starts running with the FRC as the clock source and performs an automatic clock switch to the selected clock source.