18.3.1.6 Deep Sleep Mode

In the Deep Sleep mode, the FlexRAM (SRAM) is in the Retention mode (on demand) while the CPU and peripherals (see Table 18-2 for available peripherals as wake-up source) are OFF, and no code is executed.

Deep Sleep Mode Entry

The Deep Sleep mode is entered by performing the following steps:

  1. Disable all interrupts.
  2. Set Wireless Subsystem into the Low-Power mode.
  3. Set the DSEN bit in the DSCON register.
  4. Enable the Deep Sleep wake-up source (See Table 18-2).
  5. Check for any pending interrupts and if present, abort Deep Sleep mode and service the interrupt.
  6. If there are no pending interrupts, then issue a SLEEP/WFI command from the CPU.

To minimize the chance that Deep Sleep is spuriously entered, the SLEEP/WFI command must be issued as the next instruction following the setting of the DSCON.DSEN bit. This sequence can still be interrupted by interrupts and other system latencies but does not prevent the Deep Sleep mode being entered once the SLEEP/WFI command is executed. The DSEN bit is then automatically cleared when exiting the Deep Sleep mode.

Note: The DSWSRC register clears automatically when the DSEN bit is set, regardless of whether the Deep Sleep mode is actually entered or not. Therefore, software must read this entire register after exiting the Deep Sleep mode and before re-enabling the Deep Sleep mode.

Deep Sleep Mode Exit

The Deep Sleep mode exits on any of the following events:

  1. Device exits Deep Sleep due to a wake-up event.

    1. POR event (de-assertion) on the VDD supply.

    2. DSWDT time-out (if DSWDT is enabled). When the DSWDT timer times out, the Deep Sleep mode will be

      exited.

    3. RTCC alarm (if RTCC is enabled).

    4. Assertion (0) of the (MCLR) pin.

    5. Assertion of the INT0 pin (if the interrupt was enabled before the Deep Sleep mode was entered). The polarity configuration (refer to CFGCON0.INT0P) is used to determine the assertion level (0 or 1) of the pin that causes an exit from the Deep Sleep mode.
      Note: Any interrupts pending when entering the Deep Sleep mode are cleared, and exiting from the Deep Sleep mode requires a change on the INT0 pin while in the Deep Sleep mode.
  2. The DSEN bit is automatically cleared.
  3. Read the Deep Sleep Status bit and clear it.
  4. Read the DSSEMA1 registers (optional).

  5. When

    all state-related configuration is complete, clear the DSSR bit in the DSCON register.
  6. Device releases all held logic and/or I/Os. Until this occurs, the control and data bits for the I/Os have no effects on the actual I/O state.
  7. Software resumes normal operation.