An AHB clock (CLK_QSPI_AHB) is required to clock the QSPI. In PIC32CX-BZ3, SYS_CLK is the AHB clock and can be configured in the CRU.
A FAST clock (CLK_QSPI2X_AHB) is required to clock the QSPI. This clock can be enabled and disabled in the CFGCON1 register, bit 29 (CFGCON1.QSPIDDRM). When using QSPI DDR (Double Data Rate) mode, the System Clock (SYS_CLK) must be less than or equal to 32 MHz.
PB2_CLK is the CLK_QSPI_APB clock and can be configured in CRU registers.Figure 35-2. QSPI Clock Organization
Important: The CLK_QSPI2x_AHB must be two times faster to CLK_QSPI_AHB when the QSPI is operated in the DDR mode. In Single Data Rate (SDR), the CLK_QSPI2x_AHB is not used.
The CLK_QSPI_APB, CLK_QSPI_AHB and CLK_QSPI2X_AHB, respectively, are all synchronous but can be divided by a prescaler.
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