41.8.19 Pattern Buffer
Note: The user must ensure to write this register with 16-bit
accesses only (no 8-bit writes).
| Name: | PATTBUF |
| Offset: | 0x64 |
| Reset: | 0x0000 |
| Property: | Write-Synchronized,
Read-Synchronized |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | PGVB5 | PGVB4 | PGVB3 | PGVB2 | PGVB1 | PGVB0 | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | PGEB5 | PGEB4 | PGEB3 | PGEB2 | PGEB1 | PGEB0 | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 8, 9, 10, 11, 12, 13 – PGVBx Pattern Generation
Output Value Buffer [x=0..5]
This register is the
buffer for the PGV register. If double buffering is used, valid content in this
register is copied to the PGVx register on an UPDATE
condition.
Bits 0, 1, 2, 3, 4, 5 – PGEBx Pattern Generation
Output Enable Buffer [x=0..5]
This register is the
buffer of the PGE register. If double buffering is used, valid content in this
register is copied into the PGEx register at an UPDATE
condition.
