26.8.1 Control

When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored.

For details on arbitration schemes, see Arbitration from Related Links.

These bits are not enable-protected.

Writing a ‘0’ to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled.

Setting this bit will enable the DMA module.

Writing a ‘0’ to this bit will disable the DMA module. When writing a ‘0’ during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed.

This bit is not enable-protected.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit when the DMAC module is disabled (DMAENABLE bit set to ‘0’ ), resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error.