This register configures the slew rate control bits associated with Port A.
Note: To configure the slew rate, the user must also configure the SRCON1A register associated with Port A. See Slew Rate Control Bit Settings table in the Slew Rate Control from Related Links.
Name:
SRCON0A
Offset:
0xC0
Reset:
0x0
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
SR0x
SR0x
SR0x
SR0x
SR0x
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SR0x
SR0x
SR0x
SR0x
SR0x
SR0x
SR0x
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bits 0,1,2,4,5,6,7,8,9,10,13,14 – SR0x (x = 0, 1, 2, 4, 5, 6, 7, 8, 9, 10; x = 0 for bit0 mapped to PA0, … x = 2 for bit 2, x = 4 for bit4, … x = 10 for bit 10, x = 13 for bit13, … x = 14 for bit 14 mapped to PA14) Slew Rate Control 0 for PortA.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.