1.4.1 ECC Operation in LSRAMs
(Ask a Question)LSRAMs configured in two-port mode with 33-bit data width supports ECC with single-bit error correction and dual-bit error detection (SECDED) capabilities. The LSRAMs are designed with an interleave distance of 11.52 µm (center-to-center distance) to prevent multiple bit upsets within a single word. Also, in the memory array, latch-up (SEL) is prevented by including rows of tub ties spaced no more than 8.0 m.
The ECC logic in LSRAMs generates the following flags for the user logic to take necessary action:
- SB_CORRECT: Asserted when a single-bit error is detected. If SB_CORRECT is set without the dual-bit error flag being asserted, the corrupted bit is corrected in read data output. The data scrubbing is not implemented in the ECC logic. The scrubbing must be implemented in the user logic if required.
- DB_DETECT: Asserted when a dual-bit error is detected, but not corrected. Multi-bit errors (more than two bits) produce unknown results on the flags and data outputs. If DB_DETECT is set, correction is not performed on read data output.
For more information about LSRAM ECC operation, see UG0680: PolarFire FPGA Fabric User Guide.