1.4.3 ECC Operation in PCIe
(Ask a Question)The Single Error Correction and Double Error Detection (SECDED) error reporting counters and interrupt registers display inaccurate values when ECC is enabled (default) within the PCIe hard IP block. This functional issue in the PCIe hard IP core impacts designs by incorrectly reporting single and double error counts that did not occur.
If ECC is enabled within the PCIe subsystem, ensure that the listed actions need to be taken:
- All SECDED error count registers must be ignored
- All SECDED related buffer interrupts must be disabled through the Mask registers, and associated Interrupt
- Registers must be ignored
For more information, see PCIe SECDED Reporting Defeatured in PolarFire FPGA, PolarFire SoC FPGA, and RT PolarFire FPGA.