1.4 Reset Structure

The reset structure of the design is shown in Figure 1-8. The output of the PF_POWER_INIT monitor ANDed with PLL_Lock_0 is used to reset the logic in the design. This output is combined with the following signals to reset the modules in the design:

  • The output is ANDed with O_SYS_MAC_RX_RDY to reset the COREABC and FiFo_wrapper_top module. CoreABC configures the CORE10GMAC when MAC RX is ready.
  • The output is NAND with the transceiver control signal, LANE0_RX_VAL, and is used to reset the RX path of the CORE10GMAC. The MAC RX path is held in reset until the transceiver, LANE0_RX_VAL is driven to "1".

The PF_POWER_INIT monitor output, ANDed with the transceiver control signal, LANE0_TX_STABLE, is issued to reset the TX path of the CORE10GMAC.

The MAC TX path is held in reset until the RESET_DELAY, OUT is driven to "1". The LANE0_PCS_ARST_N signal of PF_XCVR is reset using O_CORE_TX_SRESET of the CORE10GMAC.

Figure 1-8. Reset Structure