25.10.16 Channel Linked List Configuration Status Register
This channel resets on a channel reset.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHLLCFGSTATk |
| Offset: | 0x8C + k*0x50 [k=0..15] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCDAT | CTRLCRC | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PDAT | XSIZ | DSTRD | SSTRD | DSA | SSA | EVCTRL | CTRLB | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – CRCDAT CRC Data Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change the field CRCDAT. |
| 1 | CHCRCDATk.CRCDAT[31:0] is loaded from memory location BDCRCDAT |
Bit 8 – CTRLCRC Control CRC Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change the field CTRLCRC. |
| 1 | CHCTRLCRCkis loaded from memory location BDCTRLCRC. |
Bit 7 – PDAT Match Pattern Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change Registers fields PDAT or PIGN. |
| 1 | CHPDATk.PDAT[15:0] is loaded from memory location BDPDATA[15:0] and PIGN[7:0] is loaded from memory location BDPDAT[31:24]. |
Bit 6 – XSIZ Transfer Size Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change BLKSZ and CSZ. |
| 1 | CHXSIZk.BLKSZ and CHXSIZk.CSZ are loaded from BDXSIZ |
Bit 5 – DSTRD Destination Cell Stride Size Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change DSTRD |
| 1 | CHDSTRDk.DSTRD is loaded from memory location BDDSTRD |
Bit 4 – SSTRD Source Cell Stride Size Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change SSTRD |
| 1 | CHSSTRDk.SSTRD is loaded from memory location BDSSTRD |
Bit 3 – DSA Destination Start Address Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change DSA |
| 1 | CHDSAk.DSA is loaded from memory location BDDSA |
Bit 2 – SSA Source Start Address Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change SSA |
| 1 | CHDSAk.SSA is loaded from memory location BDSSA |
Bit 1 – EVCTRL EVCTRL Register Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change CHEVCTRLk |
| 1 | Control Register CHEVCTRLk is loaded from memory location BDEVCTRL |
Bit 0 – CTRLB CTRLB Register Descriptor Load
| Value | Description |
|---|---|
| 0 | Do not change CHCTRLBk |
| 1 | Control Register CHCTRLBk is loaded from memory location BDCTRLB |