37.14.1 TX Control Status Register Low for Endpoint 1-7
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TXCSRL |
| Offset: | 0x1012 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INCOMPRX | CLRDT | SENTSTALL | SENDSTALL | FLUSHFIFO | UNDERRUN | FIFONE | TXPKTRDY | ||
| Access | R/W/HS | R/W | R/W | R/W | R/W/HC | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – INCOMPRX Incomplete Packet Status bit
In anything other than Isochronous transfer, this bit will always return 0.
| Value | Description |
|---|---|
| 0 | Written by the software to clear this bit |
| 1 | The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received |
Bit 6 – CLRDT Clear Data Toggle Control Bit
| Value | Description |
|---|---|
| 0 | Do not clear the data toggle |
| 1 | Resets the endpoint data toggle to 0 |
Bit 5 – SENTSTALL Stall Handshake Status Bit
| Value | Description |
|---|---|
| 0 | Written by the software to clear this bit |
| 1 | STALL handshake is transmitted |
Bit 4 – SENDSTALL STALL Handshake Control bit
| Value | Description |
|---|---|
| 0 | Terminate stall condition |
| 1 | Issue a STALL handshake |
Bit 3 – FLUSHFIFO FIFO Flush Control bit
| Value | Description |
|---|---|
| 0 | Do not flush the FIFO |
| 1 | Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TXPKTRDY bit is cleared and an interrupt is generated. |
Bit 2 – UNDERRUN Underrun Status bit
| Value | Description |
|---|---|
| 0 | Written by software to clear this bit. |
| 1 | An IN token has been received when the TXPKTRDY bit is not set. |
Bit 1 – FIFONE FIFO Not Empty Status bit
| Value | Description |
|---|---|
| 0 | TX FIFO is empty |
| 1 | There is at least 1 packet in the TX FIFO |
Bit 0 – TXPKTRDY TX Packet Ready Control bit
The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO.