34.12.14 Pin Configuration n
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
| Port Group | Packages | ||
|---|---|---|---|
| 144 pin TQFP | 100 pin TQFP | 64 pin QFN/TQFP | |
| PORT A (GROUP 0) | PA[0:28] | PA[0:18] | PA[0:12} |
| PINCFGn Registers | n=[0-28] | n=[0-18] | n=[0-12] |
| PORT B (GROUP 1) | PB[0:26] | PB[0:17] | PB[0:10] |
| PINCFGn Registers | n=[0-26] | n=[0-17] | n=[0-10] |
| PORT C (GROUP 2) | PC[0:29] | PC[0:20] | PC[0:13] |
| PINCFGn Registers | n=[0-29] | n=[0-20] | n=[0-13] |
| PORT D (GROUP 3) | PD[0:21] | PD[0:12] | PD[0:11] |
| PINCFGn Registers | n=[0-21] | n=[0-12] | n=[0-11] |
EXAMPLE:
PORT_REGS->GROUP[2].PORT_PINCFG4 = 0x12; /* I/O pin PC4, Slew rate control enabled (4x slower), input buffer enabled */
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PINCFGn |
| Offset: | 0x40 + n*0x01 [n=0..31] |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEWLIM[1:0] | ODRAIN | PULLEN | INEN | PMUXEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:4 – SLEWLIM[1:0] Output Driver Slew Rate Selection
- Slew rate control can be used to improve signal integrity for high-speed signals if improper external HDW resistor termination was not utilized.
- If an I2C function is enabled on a pin, the corresponding PINCFGn.SLEWLIM MUST = 0x00.
- Not all pins have slew rate control. See Table 34-23 for a list.
| Value | Description |
|---|---|
| 0 | Slew rate control disabled (fast rise/fall time operation). |
| 1 | Slew rate control enabled (4x slower). |
| 2 | Slew rate control enabled (8x slower). |
| 3 | Slew rate control enabled (12x slower). |
Bit 3 – ODRAIN Open Drain Output
| Value | Description |
|---|---|
| 0 | The open drain output is disabled. |
| 1 | The open drain output is enabled. |
Bit 2 – PULLEN Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
| Value | Description |
|---|---|
| 0 | Internal pull resistor is disabled and the input is in a high-impedance configuration. |
| 1 | Internal pull resistor is enabled and the input is driven to a defined logic level in the absence of external input. |
Bit 1 – INEN Input Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the Physical Pin state when the pin is configured as either an input or output.
| Value | Description |
|---|---|
| 0 | Input buffer for the I/O pin is disabled and the input value will not be sampled. |
| 1 | Input buffer for the I/O pin is enabled and the input value will be sampled when required. |
Bit 0 – PMUXEN Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXm, m=0,...15) to enable or disable alternative peripheral control over an I/O pin direction and output drive value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output logic level via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXm is ignored. Writing '1' to this bit enables the peripheral selection in PMUXm to control the pad. In this configuration, the Physical Pin state may still be read from the Data Input Value register (IN) if PINCFGn.INEN is set.
| Value | Description |
|---|---|
| 0 | The peripheral multiplexer selection is disabled and the PORT registers control the direction and output drive value. |
| 1 | The peripheral multiplexer selection is enabled and the selected peripheral function controls the direction and output drive value. |