34.12.10 Control

Table 34-13. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRL
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 SAMPLING[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 SAMPLING[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SAMPLING[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 SAMPLING[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – SAMPLING[31:0] Input Sampling Mode

Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR).

The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.

Note: Bit 0 corresponds to Port A0/B0/C0, etc. Bit 1 to PORT A1, B1, C1, etc. All ports will not have 32 pins associated with them so some bits may not apply.
ValueDescription
0On demand sampling of I/O pin is enabled.
1Continuous sampling of I/O pin is enabled.