34.12.12 Event Input Control

There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.

Table 34-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection, Secure

Bit 3130292827262524 
 PORTEI3EVACT3[1:0]PID3[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 PORTEI2EVACT2[1:0]PID2[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PORTEI1EVACT1[1:0]PID1[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PORTEI0EVACT0[1:0]PID0[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7, 15, 23, 31 – PORTEIx PORT Event Input Enable x [x = 3..0]

ValueDescription
0The event action x (EVACTx) will not be triggered on any incoming event.
1The event action x (EVACTx) will be triggered on any incoming event.

Bits 5:6, 13:14, 21:22, 29:30 – EVACTx PORT Event Action x [x = 3..0]

These bits define the event action the PORT will perform on event input x.

Bits 0:4, 8:12, 16:20, 24:28 – PIDx PORT Event Pin Identifier x [x = 3..0]

These bits define the I/O pin on which the event action will be performed, according to the following table.

Table 34-16. PORT Event x Action ( x = [3..0] )
ValueNameDescription
0x0OUTOutput register of pin will be set to level of event.
0x1SETSet output register of pin on event.
0x2CLRClear output register of pin on event.
0x3TGLToggle output register of pin on event.
Table 34-17. PORT Event x Pin Identifier ( x = [3..0] )
ValueNameDescription
0x0PIN0Event action to be executed on PIN 0.
0x1PIN1Event action to be executed on PIN 1.
.........
0x31PIN31Event action to be executed on PIN 31.