27.9 Standby with Power Domain Gating
In standby sleep mode, the power domain core switchable (PD_CORE_SW) of a peripheral can remain in active state to perform the peripheral’s tasks. This Power Domain Gating feature is supported by all peripherals. For some peripherals, it must be enabled by writing ‘1’ to the Run in Standby bit in their respective Control A register (CTRLA.RUNSTDBY = 0x1). Refer to each peripheral chapter for details.
The following example illustrate standby with power domain gating:
TC0 Standby with Power Domain Gating
TC0 peripheral is used in counter operation mode. An interrupt is generated to wake-up the device based on the TC0 peripheral configuration. When the TC0->CTRLA.RUNSTDBY bit is set to ‘1’, it allows the TC0 peripheral to run in standby.
- Entering Standby sleep mode: As shown in figure below, PD_CORE_SW remains active. Refer to 4Power Domains, Regulators, RAMs and NVM State in Sleep Modes for details.
- Exiting Standby sleep mode: When conditions are met, the TC0 peripheral generates an interrupt to wake up the device, and the CPU can operate normally and execute the TC0 interrupt handler accordingly.
- Wake-up time:
- In this case, the VDDCORE voltage is supplied by the main voltage regulator. Therefore, global wake-up time is not affected by the regulator.
- If TC0 is running with a clock contained in the PD_CORE_PLL power domain and the dedicated SUPC->VREGCTRL.AVREGSTDBYπ = 0x1, the PD_CORE_PLL is kept on. Therefore, the global wake-up time is not affected by VREGPLL regulator.
- If TC0 is running with a clock contained in the PD_CORE_PLL power domain and the dedicated SUPC->VREGCTRL.AVREGSTDBYπ = 0x0, the PD_CORE_PLL is turned off during standby sleep mode. Therefore, the time required to activate the PD_CORE_PLL power domain must be considered as a variable for the global wake-up time.
- Note the required time to activate the PD_CORE_SW power domain must be considered also for the global wake-up time computation. Refer to Wake-up time for details.
RTC in Standby with Power Domain Gating
In this example, RTC peripheral is used to detect an overflow condition to generate interrupt to the CPU. GCLK peripheral is not used. Refer to Real Time Counter (RTC) for details. The RTC peripheral is in the PD_CORE_BU (not switchable) and there is no RUNSTDBY bit in the RTC peripheral.
- Entering Standby sleep mode: As shown in figure below, the PD_CORE_SW power domain is active. The VDDCORE voltage level is supplied by the VREGSW voltage regulator who is running in low power mode. The PD_CORE_PLL is shut-off if no clock requests are present.
- Exiting Standby sleep mode: When conditions are met, the RTC peripheral generates an interrupt to wake the device up. Successively, the PM sets PD_CORE_RAM to active state, and the main voltage regulator restarts. In the same way, if the CPU is clocked by any clock source from the PD_CORE_PLL power domain, the additional regulator restarts. Once PD_CORE_RAM and PD_CORE_PLL are in active state and both the main voltage regulator and additional regulator are ready, the CPU is able to operate normally and execute the EIC interrupt handler accordingly.
- Wake-up time:
- The required time to set the RAM power domain to active state must be considered for the global wake-up time. Refer to the Wake-up Timings for details.
- When in standby sleep mode, the GCLK peripheral is not used, allowing the VDDCORE to be supplied by the voltage regulator in low power mode to reduce power consumption
- In the same way, if no peripheral is requesting one of the PLLs clock sources, the additional regulator is not required, and it will be internally disabled to save power if SUPC ≧VREGCTRL.AVREGSTDBYπ = 0x0. Consequently, the main voltage regulator wake-up time must be considered for the global wake-up time as shown in following figure.