27.4 Functional Description
Power Domains
The device consists of the following internal power domains:
- PD_CORE_BU (Power Domain Backup). It contains the backup peripherals:
- XOSC32K - 32k oscillator
- OSCULP32K – Low Power RC
- SUPC - Supply Controller
- RSTC - Reset Controller
- RTC - Real Time Clock
- PM - Power Manager
- TRAM – Trust RAM
- PD_CORE_SW (Power Domain Switchable). It contains the CPU, FLASH and all the peripherals not located in the PD_CORE_BU.
- PD_CORE_RAM (Power Domain RAM ). It contains the System SRAM. It can be partially or fully turned OFF in standby or hibernate mode according to STDBYCFG.RAMCFG or HIBCFG.RAMCFG configuration.
- PD_CORE_USB (Power Domain USB). Dedicated power domain containing USB-PHY cells.
- PD_CORE_PLL (Power Domain PLL ). Dedicated power domain containing PLL cells.
| POWER DOMAINS | INTERNAL REGULATORS | POWER DOMAIN COMMENTS | ||||
|---|---|---|---|---|---|---|
| VREGRAM | LPVREG | VREGSW | USBVREG | PLLVREG | ||
| PD_CORE_BU | X | X | — | — | — | Backup power domain powered by
VREGRAM regulator except in BACKUP mode when LPVREG is the power
source. Includes peripherals:
|
| PD_CORE_SW | — | — | X | — | — | CPU core and peripherals power domain other than those in PD_CORE_BU, (backup Domain) |
| PD_CORE_RAM | X | — | — | — | — | System SRAM Power domain |
| PD_CORE_USB | — | — | — | X | USB PHY power domain | |
| PD_CORE_PLL | — | — | — | — | X | Powers the PLL (analog) power domain |
| DOMAIN REGULATOR CONTROLS | ||||||
| SUPC.AVREGEN {x,y] | — | — | — | X | X | USB and PLL regulator enable/disable |
| STANDBY MODE | ||||||
| SUPC.AVREGSTDBY[x,y ] | — | — | — | X | X | USB and PLL regulator behavior control in STDBY mode |
| PM.STDBYCFG.RAMCFG | X | — | — | — | — | Selects whether system SRAM powered or not powered in STANDBY mode. |
| PM.STDBYCFG.LPRAM | X | — | — | — | — | Selects if SRAM interface logic is powered or not powered in STANDBY mode. |
| HIBERNATE MODE | ||||||
| PM.HIBCFG.RAMCFG | X | — | — | — | — | Selects whether system SRAM powered or not powered in HIBERNATE mode. |
| PM.HIBCFG.LPRAM | X | — | — | — | — | Selects if SRAM interface logic is powered or not powered in HIBERNATE mode. |
Note:
- Product specific, see SUPC.VREGCTRL register for confirmation.