27.5 Sleep Modes

Important: To facilitate the use of sleep modes, the following conditions must be met:

PLL0 must be dedicated to the CPU
PLL0 GCLK0 must be stepped down in ≦ 75 MHz increments to ≦ 75 MHz MCLK frequency prior to entering IDLE or STANDBY sleep mode
PLL0 GCLK0 must be stepped up to the desired nominal operating frequency in ≦ 75 MHz maximum increments after exiting IDLE or STANDBY sleep modes
The GCLK0 MCLK frequency step delay for both of these processes needs to be ≧ 1 us/step

The device can be set in a sleep mode (idle, standby, hibernate, backup and off). In sleep mode, the CPU is stopped, and the peripherals are either active or idle, according to the sleep mode depth. The sleep modes and their effects on the clocks’ activity, the regulators, the power domains state, the RAMs and NVM state are described in the table and the following sections:

Table 27-3. Power Manager Sleep Modes
Sleep Modes	MCLK Main Clock	CPU	AHBx/APBx Clocks	GCLK0 clock	Other GCLK clocks	Oscillators			Regulators					Power Domains State					SRAM	NVM
Sleep Modes	MCLK Main Clock	CPU	AHBx/APBx Clocks	GCLK0 clock	Other GCLK clocks	RUNSTDBY	ONDEMAND		LPVREG	VREGSW	VREGRAM	VREGPLL	VREGUSB	PD_CORE_BU	PD_CORE_SW	PD_CORE_RAM	PD_CORE_USB	PD_CORE_PLL	SRAM	NVM
Active	Run	Run	Run	Run	Run if Requested. (RiR)	X	0	Run	On ⁽⁹⁾	On	On	On⁽¹⁾		Active	Active		On⁽¹⁾		Active	Active
Active	Run	Run	Run	Run	Run if Requested. (RiR)	X	1	RiR		On	On	On⁽¹⁾			Active		On⁽¹⁾		Active	Active
IDLE	Run	Stop	Stop⁽²⁾	Run	RiR	X	0	Run		On	On	On⁽¹⁾			Active		On⁽¹⁾		Active	Active
IDLE	Run	Stop	Stop⁽²⁾	Run	RiR	X	1	RiR		On	On	On⁽¹⁾			Active		On⁽¹⁾		Active	Active
STANDBY	RiR	Stop	Stop⁽²⁾	Stop ⁽²⁾	Run	0	0	Run		(8, 10)		On⁽³⁾			Active	Full or 32 KB retention ⁽⁶⁾	On(3)		(11)	LPM⁽⁴⁾
					RiR	0	1	RiR
					Run	1	0	Run
					RiR	1	1	RiR
HIBERNATE	Stop	Stop	Stop	Stop						Off	(8,10)	Off			Off	Full or 32 KB retention ⁽⁷⁾	Off		(12)	Off
BACKUP	Stop	Stop	Stop	Stop						Off					Off				Off	Off
OFF	Off	Off	Off	Off					Off					Off					Off	Off

Note:

Run if enabled (SUPC.VREGCTRL.AVREGENx = 0x1), or for VREGUSB, (i.e., PD_CORE_USB), only, if USB.CTRLA.ENABLE=1.
Stop except if running during Sleepwalking.
Run if enabled (SUPC.VREGCTRL.AVREGENx = 0x1) and run-in standby feature is enabled (SUPC.VREGCTRL.AVREGSTDBYx = 0x1).
This is product specific. In some devices NVM, (Non Volatile Memory), has a separate and independent low-power configuration that is defined by NVMCTRL.CTRLB.SLEEPPRM or FCR.CTRLB.SLP if they exist.
I/O are in high-impedance mode except the RESET_N pad which is still in input mode and can detect a reset to wake-up the chip.
Refer to PM.STDBYCFG.RAMCFG and section: Standby Sleep Mode.
Refer to PM.HIBCFG.RAMCFG and section: Hibernate Sleep Mode.
The low power voltage regulator (LPVREGC) supplies the VDDCORE_BU in backup sleep mode.
Behavior dependent on PM.STDBYCFG.RAMCFG.
Behavior dependent on PM.HIBCFG.RAMCFG.

Idle Sleep Mode

The IDLE mode allows power optimization with the fastest wake-up time.

The CPU is stopped, the logic is retained, and peripherals are still working. Synchronous clocks are stopped except when requested. As the main clock source is still running, wake-up time is minimal. The GCLK clocks, regulators and RAM are not affected by the idle sleep mode and operates normally.

Any interrupt event for an enabled interrupt source will cause the MCU to exit IDLE mode and return to ACTIVE mode and vector to the designated interrupt service routine provided that the interrupt event is a higher priority than the current interrupt priority before entry into IDLE mode.

Table 27-4.
USB & PLL		IDLE MODE
SUPC.VREGCTRL.AVREGEN [x:y]	CTRLA.ENABLE	IDLE MODE
		VREGRAM		LPVREG		VREGSW		VREGUSBn		VREGPLL
		Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power
0x0	0	1.2v	NOM	0.8v	NOM	1.2v	NOM	OFF	—	OFF	—
0x0	1⁽¹⁾	1.2v	NOM	0.8v	NOM	1.2v	NOM	1.2v	NOM	OFF	—
0x3	0	1.2v	NOM	0.8v	NOM	1.2v	NOM	1.2v	NOM	1.2v	NOM
0x3	1⁽¹⁾	1.2v	NOM	0.8v	NOM	1.2v	NOM	1.2v	NOM	1.2v	NOM

Note:

USB.CTRLA.ENABLE will override USB regulator control if disabled in SUPC.VREGCTRL.AVREGEN register and force it to be enabled and active ON.

Standby Sleep Mode

The standby sleep mode is the lowest power configuration while keeping the state of the logic and the content of the RAM.

The CPU is stopped as well as the peripherals. The logic is retained, and power domain gating can be used to turn off the PD_CORE_RAM power domain fully or partially. In this mode, all clocks are stopped except those configured to perform sleepwalking tasks. The clocks can also run on request or at all times, depending on their on-demand and run-in-standby settings.

Additionally, it is possible to scale STANDBY power further with the combination use of PM.STDBYCFG.LPRAM=1 and PM.STDBYCFG.RAMCFG=1 for minimizing SRAM power consumption by powering down various SRAM sections.

Refer to the SUPC.VREGCTRL, SUPC.VREFCTRL, and PM.STDBYCFG register for more details.

Refer to Sleepwalking for more details on Sleepwalking feature.

Table 27-5. SLEEP Standby Mode MCU Power Distribution Summary
USB & PLL		STANDBY MODE
SUPC.VREGCTRL.AVREGEN [x:y]	SUPC.VEGCTRL.AVREGSTDBY [x:y]	STANDBY MODE
		VREGRAM		LPVREG		VREGSW		VREGUSBn		VREGPLL
		Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power
0	0	1.2v	NOM	0.8v	NOM	1.2v	NOM	OFF⁽¹⁾	X	OFF⁽¹⁾	X
0	1	1.2v	NOM	0.8v	NOM	1.2v	NOM	OFF⁽¹⁾	X	OFF⁽¹⁾	X
1	0	1.2v	NOM	0.8v	NOM	1.2v	NOM	OFF⁽¹⁾	X	OFF⁽¹⁾	X
1	1	1.2v	NOM	0.8v	NOM	1.2v	NOM	1.2v	NOM	1.2v	NOM

Note:

If USB.CTRLA.ENABLE=1, it will override any USB SUPC.VREGCTRL.AVREGEN regulator disable setting and force the USB regulator on.
These bits are product dependent. See SUPC.VREGCTRL and SUPC.VREFCTRL registers if implemented.

Figure 27-3. System SRAM Standby Sleep Mode Extended Features

Hibernate Sleep Mode

The HIBERNATE mode allows achieving lower power consumption than STANDBY mode.

The device is entirely powered off except for:

The PD_CORE_BU power domain to allow few features to run (RTC, 32kHz clock sources, and wake-up from external pins)
The PD_CORE_RAM power domain that can be retained according to HIBCFG register configuration

All PM registers are reset to their default value when entering hibernate sleep mode except the I/O retention bit in CTRLA.IORET. If CTRLA.IORET =1, the I/O values are retained on entry and exit from HIBERNATE mode.

Table 27-6. SLEEP Hibernate Mode MCU Power Distribution Summary
USB & PLL		HIBERNATE MODE
SUPC.VREGCTRL.AVREGEN [x:y]	CTRLA.ENABLE	HIBERNATE MODE
		VREGRAM⁽¹⁾		LPVREG ⁽²⁾		VREGSW		VREGUSBn		VREGPLL
		Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power
X	X	1.2v	NOM	0.8v	NOM	OFF	--	OFF	--	OFF	--
X	X	1.2v	LOW	0.8v	NOM	OFF	--	OFF	--	OFF	--

Note:

In HIBERNATE mode regulator VREGRAM is ON and supplies power to:
- XOSC32K - 32k oscillator
- OSCULP32K – Low Power RC
- SUPC - Supply Controller
- RSTC - Reset Controller
- RTC - Real Time Clock
- PM - Power Manager
- TRAM – Trust RAM
- System SRAM depending on status of PM.HIBCFG.RAMCFG which defines SRAM retention policy
Low power regulator LPVREG is always on but does not supply power to any logic except in BACKUP mode.
Product specific. See SUPC.VREGCTRL and SUPC.VREFCTRL registers if implemented.

Figure 27-4. SRAM Hibernate Mode Flow

Backup Sleep Mode

The BACKUP mode allows achieving the lowest power consumption aside from OFF mode.

The device is entirely powered off except for:

The PD_CORE_BU power domain to allow few features to run (RTC, 32kHz clock sources, and wake-up from external pins)
The PD_CORE_RAMρ power domain that can be retained according to HIBCFG register configuration

All PM registers are reset to their default value when entering Backup sleep mode except the I/O retention bit in CTRLA.IORET. If CTRLA.IORET =1, the I/O values are retained on entry and exit from BACKUP mode.

Table 27-7. SLEEP Backup Mode MCU Power Distribution Summary
USB & PLL		BACKUP MODE
SUPC.VREGCTRL.AVREGEN [x:y]	USB/PLL CTRLA.ENABLE	VREGRAM		LPVREG ⁽¹⁾		VREGSW		VREGUSBn		VREGPLL
SUPC.VREGCTRL.AVREGEN [x:y]	USB/PLL CTRLA.ENABLE	Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power	Voltage	Power
X	X	OFF	—	0.8v	NOM	OFF	—	OFF	—	OFF	—

Note:

All regulators, other than the LPVREG regulator, are disabled and OFF and all system SRAM contents are lost In BACKUP mode only regulator LPVREG is ON and supplies power to the backup domain containing the following:
- XOSC32K - 32k oscillator
- OSCULP32K – Low Power RC
- SUPC - Supply Controller
- RSTC - Reset Controller
- RTC - Real Time Clock
- PM - Power Manager
- TRAM – Trust RAM

Off Sleep Mode

The OFF mode allows achieving the lowest power consumption. The device internally is powered off and all internal regulators are disabled during OFF mode.

PIC32CZ CA80/CA90 Family

27.5 Sleep Modes

Idle Sleep Mode

Standby Sleep Mode

Hibernate Sleep Mode

Backup Sleep Mode

Off Sleep Mode