27.11 Debug Operation

When the CPU is halted in debug mode, the PM continues normal operation. If Standby sleep mode is requested by the system while in debug mode, the power domains are not turned off. Consequently, power measurements while in debug mode are not relevant.

If Hibernate or Backup sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the hibernate or backup mode upon a reset condition, the core domains are reset except the debug logic, allowing users to keep using their current debug session.

Important: Power measurements while in debug mode are irrelevant.
Table 27-9. PM Functional Configuration Summary
SLEEPCFG

(SLEEPMODE)

STDBYCFGHIBCFGCTRLAPOWER DOMAINSDESCRIPTION
PD_CORE_BUPD_CORE_SWPD_CORE_RAMPD_CORE_USBPD_CORE_PLL
RAMCFGLPRAMRAMCFGLPRAMIORET
IDLEXXXXXOnOnOnOn(1)On
  • CPU halted
  • Peripherals clock sources, active
  • SRAM retained
STANDBY00XXXOnOnOn(2)(2)
  • CPU Halted, Peripherals (3)
  • No SRAMs contents retained
01OnOnOn(2)(2)
  • CPU Halted, Peripherals (3)
  • No SRAMs contents retained
10OnOnOn(2)(2)
  • CPU Halted, Peripherals (3)
  • All SRAM contents retained
11OnOnOn(2)(2)
  • CPU Halted, Peripherals(3)
  • All SRAM contents retained
HIBERNATEXX000OnOffOffOffOff
  • CPU halted, RTC & XOSC32K active
  • All SRAMs contents retained
  • I/O line values retained on entry/exit
1OnOffOffOffOff
  • CPU halted, RTC & XOSC32K active
  • All SRAMs contents retained
  • I/O line values retained on entry/exit
010OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • All SRAMs contents retained in low power mode
  • I/O line values retained on entry/exit
1OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • All SRAMs contents retained in low power mode
  • I/O line values retained on entry/exit
100OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • No SRAM contents retained
  • I/O line values retained on entry/exit
1OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • No SRAM contents retained
  • I/O line values retained on entry/exit
110OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • No SRAM contents retained in low power mode
  • I/O line values retained on entry/exit
1OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • No SRAM contents retained in low power mode
  • I/O line values retained on entry/exit
BACKUPXXXX0OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • All SRAM contents lost; TRAM retained
  • I/O line values retained on entry/exit
1OnOffOffOffOff
  • CPU halted,RTC & XOSC32K active
  • All SRAM contents lost; TRAM retained
  • I/O line values retained on entry/exit
OFFXXXXXOffOffOffOffOff
  • Everything powered down, reset required to exit
  • I/O line values NOT retained
  • All SRAM & TRAM contents lost
Note:
  1. On if USB.CTRLA.ENABLE=1 enabled.
  2. Dependent on the state of SUPC.VREGCTRL.AVREGSTDBY[x] and SUPC.VREGCTRL.AVREGEN[x]. Powered ON =‘1’, OFF =‘0’, (i.e., default), and system in STANDBY mode.
    Note: If either peripheral CTRLA.ENABLE=1, respective regulator is forced ON regardless of SUPC.VREGCTRL register settings in RUN ACTIVE, IDLE or STANDBY mode.
  3. PeripheralsRUNSTANDBYON DEMAND
    Active00
    Run If Requested01
    Active10
    Run If Requested11

Power Domain Module Asset Summary

  • PD_CORE_BU

    Backup Power Domain: VREGRAM and LPVREG)

    • XOSC32K - 32k oscillator
    • OSCULP32K – Low Pwr RC
    • SUPC - Supply Controller
    • RSTC - Reset Controller
    • RTC - Real Time Clock
    • PM - Power Manager
    • TRAM – Trust RAM
  • PD_CORE_SW (Core Power Domain: VREGSW)
    • CPU
    • Peripherals
  • PD_CORE_RAM (SRAM Power Domain)
    • SRAM
  • PD_CORE_USB (USB Power Domain)
    • USB Digital Logic, not USB PHY
  • PD_CORE_PLL (PLL Power Domain)
    • PLL Power
Table 27-10. Lowest Sleep Power Modes Settings from Highest to Lowest (Left to Right)
CONTROLPM.SLEEPCFG.SLEEPMODE=0x2

IDLE MODE

PM.SLEEPCFG.SLEEPMODE=0x4

STANDBY MODE

PM.SLEEPCFG.SLEEPMODE=0x5

HIBERNATE MODE

PM.SLEEPCFG.SLEEPMODE=0x6

BACKUP MODE

PM.SLEEPCFG.SLEEPMODE=0x7

OFF MODE

COMMENTS
STANDBY
PM.STDBYCFG.RAMCFGX1XXXSRAM powered off in STANDBY
PM.STDBYCFG.LPRAMX1XXXSRAM interface powered off in STANDBY
SUPC.VREGCTRL.AVREGSTDBY[x,y]X0x0XXXPLLn and/or USBn regulator STANDBY mode enable
SUPC.VREGCTRL.AVREGEN[x,y]0x00x0XXXPLLn and/or USBn regulator(s) disabled.
Note: Requires USB.CTRLA.ENABLE=0 and PLL.CTRLA.ENABLE=0.
AUXILIARY Features
TRAM.CTRLA.ENABLE (1)0000X0 = Trust RAM Contents lost
RTC.CTRLA.ENABLE (1)0000X0 = RTC and Tamper features disabled.

Also, no RTC BACKUP mode wake.

OSC32KCTRL.XOSC32K.ENABLE (1)0000X0 = XOSC32K disabled, no RTC, RTC BACKUP /

HIBERNATE mode wake or tamper features

unless using OSCULP32K as clock source.

OSCCTRL.PLLxCTRL.ENABLE00XXXPLLx disabled
USB.CTRLA.ENABLE00XXXUSBx disabled
HIBERNATE
PM.HIBCFG.RAMCFGXX1XXSRAM powered off in HIBERNATE
PM.HIBCFG.LPRAMXX1XXSRAM interface powered off HIBERNATE
Note:
  1. User optional. Note RTC and tamper detect requires XOSC32K or alternately OSCULP32K.