27.8 Wake-Up Time
As shown in the following figure, total wake-up time depends on:
- Latency due to reference and regulator effect: As an example, if the device is in Standby sleep mode using the voltage regulator VREGSW in low-power mode, the voltage level is lower than the one used in active mode. When the device wakes up, it takes a certain amount of time for the main regulator (VREGSW and VREGRAM) to transition to the voltage level corresponding to active mode, causing additional wake-up time. The low-power to full-power mode delay of the reference and regulator should also be added.
- Latency due to Power Domain Gating: Usually, wake-up time is measured with
the assumption that the power domains are already active. When using Power Domain
Gating, changing a power domain from OFF to active state will take a certain time.
If all power domains were already in active state in standby sleep mode, this
latency is zero. Important: Please refer to the Wake-Up Timings chapter in the Electrical Characteristics section for more details.
- Latency due to the CPU clock source wake-up time.
- Latency due to the NVM wake-up time from low-power mode.