25.7.5 Channel Priorities

The DMA provides arbitration between channels requesting access to the DMAW or DMAR ports. Each port arbitrates between channel access requests based on the channel priority group (PRI) and then between the channel natural order.

The PRI ranges from 1 to 4 where 4 specifies the highest priority available. The priority is set by the CHCTRLBk.PRI register field. Arbitration between priority groups takes place after each transaction on a port. If a channel with a priority set to 0 is actively transferring a cell, a higher priority channel can interrupt the cell transfer to gain access to the port. All channels requests with a higher priority group are processed before considering the next lower priority group.

The DMA defines a fixed natural priority between channels within the same priority group. Fixed natural priority defines a channel with a higher channel number as having a higher priority. For example, channel 10 has a higher priority than channel 0 through 9. Arbitration for resources between these channels always takes place at a cell transfer boundary. Once the current channel completes a cell transfer the DMA will arbitrate access to the channel with largest channel number k in the same priority group that has requested access to the port.

The DMA generates four interrupts, one for each priority group. The interrupt status register INTSTAT4 reports which of the channels assigned to priority four have pending interrupts. Similarly, INTSTAT3, INTSTAT2 and INTSTAT1 report which channels have pending interrupts for priority three, two, and one.

The auxiliary event system trigger can be configured to increase a channels priority. When CHEVCTRLk.EVAUXIE=1 and CHEVCTRLk.EVAUXACT=1, on each rising edge of the auxiliary event system trigger, the DMA increments the channel priority by one until the channel is at the highest priority. The value read back from CHCTRLBk.PRI reflects the channels current priority level.